The present invention relates to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits that include series-parallel type analog-to-digital converters having analog signal processing circuits.
A series-parallel type analog-to-digital (A/D) converter includes an upper rank comparator, which performs A/D conversion of upper rank bits, and a lower rank comparator, which performs A/D conversion of lower rank bits. The upper rank comparator samples analog input signals and compares the sampled signals with an upper rank reference voltage signal. The lower rank comparator samples analog input signals and compares the sampled signals with a lower rank reference voltage signal, which is based on the comparison result of the upper rank comparator. The A/D converter combines the comparison results of the upper and lower rank comparators to generate a digital signal. Thus, the sampling level of the upper rank comparator and that of the lower rank comparator must be substantially the same. The upper and lower rank comparators must perform sampling at precisely the same timing to obtain sampling levels that are substantially the same. However, differences in the load conditions of sample and hold (S/H) control signals, differences in the lengths of wires, and other factors cause unsynchronized sampling. This results in the upper and lower rank comparators sampling different analog input signals and affects the linearity of signals when combining the output signals of the upper rank and lower rank comparators.
FIG. 1 is a schematic circuit diagram showing a prior art series-parallel type comparator 10. The A/D converter 10 includes an upper rank comparator 11 and a lower rank comparator 12. The upper rank comparator 11 includes voltage comparators CM.sub.U1 -CM.sub.Um, the number m of which corresponds to the number of upper rank bits in the digital signal. The lower rank comparator 12 includes voltage comparators CM.sub.L1 -CM.sub.Ln, the number n of which corresponds to the number of lower rank bits. The voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln are chopper type voltage comparators. Each voltage comparator CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln samples an analog input signal V.sub.in and compares the sampled level with reference voltages V.sub.U1 -V.sub.Um, V.sub.L1 -V.sub.Ln, respectively.
FIG. 3 is a schematic circuit diagram showing the voltage comparator CM.sub.U1. Since each voltage comparator CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln has the same structure, only the voltage comparator CM.sub.U1 will be described in detail.
The voltage comparator CM.sub.U1 includes switches SW1-SW3, a capacitor C1, an inverter 13, and a flip-flop (FF) 14. The input terminals which receive the analog input signal V.sub.in and the reference voltage V.sub.U1 are connected to a first input terminal (node N1) of the capacitor C1 via the switches SW1, SW2, respectively. The switches SW1, SW2 are opened and closed in accordance with control signals S1u, S2u, respectively. The control signals S1u, S2u are output from a control signal generator (not shown). The respective switches SW1, SW2 are closed when the control signals S1u, S2u are high (H-level).
The capacitor C1 has a second terminal (node N2), which is connected to the data input terminal of the FF 14 via the inverter 13. The switch SW3 is opened and closed in accordance with the control signal S1u. The switch SW3 closes when the control signal S1u is high. The FF 14 latches the input signal in response to the control signal S2u and outputs a latch signal Out.
FIG. 4 is a timing chart showing the operation of the voltage comparator CM.sub.U1. If the control signal S1u is at the H-level, or is "high", while the control signal S2u is at the L-level, the switches SW1, SW3 are ON and the switch SW2 is OFF. In this state, the inverter 13 is biased at a threshold voltage Vt and electric charge (C0.times.(V.sub.in -Vt)) is stored in the capacitor C1. C0 represents the capacitance value of the capacitor C1 and V.sub.in represents the voltage of the analog input signal. This operation is referred to as auto zero, during which the analog input signal V.sub.in is stored in the capacitor C1 when the voltage comparator CM.sub.U1 is biased at the threshold voltage.
When the control signal S1u shifts to the L-level and the control signal S2u shifts to the H-level, the switches SW1, SW3 are opened and the switch SW2 is closed. In this state, the node N2 enters an electrically floating state. Thus, according to the charge conservation law, the charge stored in the capacitor C1 does not change. The application of the upper rank reference voltage V.sub.U1, instead of the analog input signal V.sub.in to the node N1, or the capacitor C1, sets a potential V2 at the node N2 at Vt+V.sub.U1 -V.sub.in since charge is conserved in the capacitor C1. In other words, the potential V2 changes from the threshold voltage Vt by (V.sub.U1 -V.sub.in). The voltage V2 is reverse-amplified by the inverter 13 and a potential having a level which logic value can sufficiently be distinguished by the FF 14 is generated. The FF14 is strobed when the potential at the node N3 is stabilized (final point during comparison) to generate a logic signal Out.
Accordingly, the A/D converter 10 operates as shown in FIG. 2. If the control signals S1u, S1v are at the H-level, while the control signals S2u, S2v are at the L-level, the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln of the upper and lower rank comparators 11, 12 each performs the auto zero operation, while receiving the analog input signal V.sub.in. Afterward, when the control signals S1u, S2u shift to the L-level, each voltage comparator CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln stores the voltage of the analog input signal V.sub.in just before the control signals S1u, S2u shift from the H-level to the L-level.
In response to an H-level control signal S2u, the upper rank comparator 11 compares the analog input signal V.sub.in with the upper rank reference voltages V.sub.U1 -V.sub.Um and A/D converts the upper rank bits, while designating the lower rank reference voltages V.sub.L1 -V.sub.Ln of the lower rank comparator 12 based on the comparison results.
After performing the auto zero operation simultaneously with the upper rank comparator 11, the lower rank comparator 12 shifts all of the switches SW1-SW3 to OFF (i.e., open) and stores the analog input signal V.sub.in while waiting until the upper rank comparator 11 determines the lower rank reference voltages V.sub.L1 -V.sub.Ln (i.e., until the upper rank bits are determined). The lower rank comparator 12 then compares the analog input signal V.sub.in with the lower rank reference voltages V.sub.L1 -V.sub.Ln and A/D converts the lower bits. The A/D converter 10 combines the upper rank bits from the upper rank comparator 11 with the lower rank bits from the lower rank comparator 12 and generates an A/D converted signal.
The upper and lower rank comparators 11, 12 must simultaneously shift from a sampling state to a holding state in order to receive analog input signals having the same level during sampling. However, it is impossible to control every switch SW1 of the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln at the same timing. With reference to FIG. 2, the sampling tolerance voltage between the upper and lower rank comparators 11, 12 is denoted as Ve. If S represents the changing rate of the analog input signal V.sub.in and te[ns] represents the sample and hold timing tolerance between the upper rank comparator 11 and the lower rank comparator 12, S.times.te represents the sampling tolerance voltage Ve. Accordingly, the timing tolerance te that is allowed decreases as the changing rate S increases. In other words, the sampling tolerance of the upper and lower rank comparators 11, 12 is narrowed.
The arrangement of a sample and hold (S/H) circuit upstream of the A/D converter 10 shifts the changing rate S of the analog input signal to a value close to zero and allows the sampling level of the upper and lower rank comparators 11, 12 to be substantially the same. However, an S/H circuit includes an amplifier and thus has a shortcoming in that the sampling voltage changes in accordance with the characteristic (speed) of the amplifier.
FIG. 5 is a schematic circuit diagram showing an A/D converter 20, which takes samples of the same level, without employing an A/D converter 10, which incorporates an amplifier (refer to Masumi Kasahara et al., "CMOS 9 Bit 25 MHz 100 mW A-D converter," Denshi Jouhou Tsuushin Gakkai, ICD91-87, pp. 43-47).
The A/D converter 20 has a switch SWt, which is connected between switches SW1 of the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln and the analog input signal V.sub.in. The upper and lower rank comparators 11, 12 receive an internal analog signal V.sub.in0, which has the potential of the node N4 between the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln and the switch SWt. A control signal St sent from a control signal generator (not shown) shifts the switch SWt between ON and OFF. This results in each voltage comparator CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln storing the same level of the internal analog signal V.sub.in0.
More specifically, as shown in FIG. 6, if the control signals S1u, S1v are at the H-level, the upper and lower rank comparators 11, 12 perform the auto zero operation based on the internal analog signal V.sub.in0. In this state, the potential of the internal analog signal V.sub.in0 is substantially the same as the analog input signal V.sub.in since the switch SWt is ON. Accordingly, the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln perform the auto zero operation based on the analog input signal V.sub.in.
If the switch SWt is subsequently shifted to OFF, the internal analog signal V.sub.in0 becomes constant. Accordingly, the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln store the potential of the analog input signal V.sub.in just before the switch SWt shifts to OFF. That is, the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln store a constant internal analog signal V.sub.in0. Therefore, the upper and lower rank comparators 11, 12 store substantially the same potential even if the fall timing of each of the control signals S1u, S1v differs from one another.
As described above, the switch SWt is shifted to OFF before the upper and lower rank comparators 11, 12 shift from a sampling state to a holding state (i.e., the switches SWl of the voltage comparators CM.sub.U1 -CM.sub.Um, CM.sub.L1 -CM.sub.Ln being shifted to OFF). Accordingly, the changing rate S of the analog input signal V.sub.in is substantially zero.
However, the upper and lower rank comparators 11, 12 are connected to each other by the same wire. Thus, if the switch SWt is shifted to OFF, the node N4 is unaffected by the analog input signal V.sub.in. That is, the node N4 enters a floating state. In the floating state, the lower rank comparator 12 (or the upper rank comparator 11) is affected by the noise produced during the switching (shifting between the sampling state and the holding state) of the upper rank comparator 11 (or the lower rank comparator 12). Furthermore, the wiring volume of a circuit having a switch is smaller than that of a circuit having no switches. Hence, the voltage fluctuation of the analog input signal V.sub.in increases when switching noise is produced in a circuit having a switch. This increases errors in the digital signal generated by the A/D converter 20 and increases the error rate.
To prevent an increase in the error rate, redundancy may be employed for the conversion operation of a lower rank comparator in order to digitally compensate for the sampling error based on the results of the comparison of the lower rank comparator (refer to N. Fukushima et al., "A CMOS 40 MHz 8b 105 mW two-step ADC", ISSCC Dig, Tech. Papers, February, 1989, pp. 14-15). The employment of redundancy allows for compensation within a certain sampling error range. However, if the level of the analog input signal is relatively large, the sampling error exceeds the range that can be compensated. This affects the linearity of the digital signals.